GROSSE, Daniel; FEY, Goerschwin; DRECHSLER, Rolf. Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electronic Communications of the EASST, [S. l.], v. 62, 2013. DOI: 10.14279/tuj.eceasst.62.860. Disponível em: https://eceasst.org/index.php/eceasst/article/view/2077. Acesso em: 21 nov. 2024.